Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with buried gates.
As the sizes of semiconductor devices shrink, the structure of word lines is changed from a structure where the word lines are positioned in the upper portion of a silicon substrate to a structure where the word lines are positioned in the lower portion of a silicon substrate. This process of forming word lines in the lower portion of a silicon substrate is referred to as a buried gate process.
FIGS. 1A to 1E are cross-sectional views illustrating a conventional method for fabricating buried gates.
Referring to FIG. 1A, an isolation layer 12 is formed in a semiconductor substrate 11, and then a hard mask pattern 13 is formed.
Referring to FIG. 1B, trenches 14 are formed by etching the semiconductor substrate 11 and the isolation layer 12 by using the hard mask pattern 13 as an etch barrier. Herein, the etched isolation layer 12 will be referred to as isolation pattern 12A.
Referring to FIG. 1C, an oxidation process is performed to form a gate insulation layer 15, and then a titanium nitride layer 16 and a tungsten layer 17 are deposited as a gate conductive layer.
Referring to FIG. 1D, a chemical mechanical polishing (CMP) process is performed for planarization, and then buried gates (BG) are formed by recessing the titanium nitride layer 16 and the tungsten layer 17 to a predetermined depth through a plasma dry etch process. Herein, the recessed titanium nitride layer 16 and tungsten layer 17 will be referred to as titanium nitride pattern 16A and tungsten pattern 17A.
Referring to FIG. 1E, the hard mask pattern 13 is removed.
According to the above-described conventional method, however, the titanium nitride layer 16 and the tungsten layer 17 may be recessed at least approximately 600 Å to approximately 650 Å during the plasma dry etch process for forming the buried gates. Therefore, some of the gate insulation layer 15 may be lost during the plasma dry etch process.
In particular, the gate insulation layer 15 at the top corners of each trench may be over-etched (see reference symbol ‘A’ of FIG. 1D) during the plasma dry etch process. In other words, the remaining gate insulation layer at the top corners of each trench may become thinner, and thus the refresh characteristic of a semiconductor device may deteriorate.
FIG. 2 is a photograph of a resultant structure after the buried gates are formed according to the conventional technology. The photograph shows the gate insulation layer becoming thin at the top corner ‘A’ of a trench.
Plasma damage which includes the thinning of a gate insulation layer, e.g., gate oxide layer, at the top corner of a trench may be one of the factors which deteriorate the refresh characteristic.